1. Field of the Invention
The present invention relates to a delay verification device for a logic circuit represented according to graph algorithms and a delay verification method therefor and, more particularly, to a delay verification device which is capable of conducting delay verification processing for a large-scale logic circuit at a high speed and a delay verification method therefor.
2. Description of the Related Art
One of the one conventional techniques related to delay verification of a logic circuit of this kind is disclosed in, for example, Japanese Unexamined Patent Publication (Kokai) No. Heisei 3-292573, entitled "Logic Design Verification System". This literature recites a delay verification technique for converting initial design data regarding a logic circuit into a logic circuit, searching the converted logic circuit for signal paths from its input to its output to compute a delay time of each signal path, and comparing the delay time as a verification result with a preset standard delay time to modify the initial design data based on the determination results.
Because the above-described conventional logic design verification system automatically conducts all the processing for delay verification of logic initial design data as well as analyses and modification, accurate and efficient logic verification is possible without the operator's assistance.
The system, however, has a drawback that processing time is too long to verify delays of a large-scale logic circuit because the system conducts delay verification for the entire logic circuit whose delay time is to be verified.
Among other techniques regarding delay verification of logic circuits are, for example, those disclosed in Japanese Unexamined Patent Publication (Kokai) No. Showa 64-66578, entitled "Delay Analysis System for Logic Circuit", and Japanese Unexamined Patent Publication (Kokai) No. Heisei 2-231646, entitled "Delay Analysis System for Logic Circuit". These literatures recite a delay verification technique for determining whether a path whose delay time exceeds a limiting value is a meaningless redundant path on a logic circuit according to the path activation method and removing a redundant path from a delay analysis result list according to the determination results to reduce a time required for determining whether a delay analysis result is good or bad and a technique for displaying only the components that are contributing factors to cause a delay time of a path to exceed a delay time limiting value to simplify modification.
The above-described conventional techniques have drawbacks that speed-up of delay verification after layout has a limit because none of these techniques makes the most of the delay state of a logic circuit prior to layout.